Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics

The self-assembly of nanoelectronic devices provide an opportunity to achieve unprecedented density and manufacturing scale in the post-Moore’s Law era. Bottom-up DNA self-assembly has emerged as a promising technique towards achieving this vision and it has been used to demonstrate precise patterning and functionalisation at resolutions below 20 nm. However, a lack of understanding of fabrication defects and their impact on circuit behaviour are major obstacles to the eventual application of these substrates to circuit design. The authors present a classification of defects observed in our experimental work on self-assembled nanostructures. Atomic force microscope (AFM) images are used to study these defects and determine their relative frequencies. The authors connect these defects to fault models and predict their likely impact on the behaviour of logic gates. Based on simulation program with integrated circuit emphasis simulation data for proposed layouts, the authors conclude that there is a predictive connection between faulty logic behaviour and physical defects for future DNA self-assembled nanoelectronics. This work will be useful in predicting the potential success of defect-tolerance techniques for DNA self-assembled nanoelectronic substrates.